As integrated circuits scale to finer feature sizes, (e.g., with features at or below 45 nm), process variations become increasingly difficult to capture with traditional modeling techniques. Understanding statistical variations has become increasingly important in design efforts to ensure manufacturability and improve parametric yield. Mismatch variation between individual devices is particularly important, so management of mismatch variation impact on circuit performance variation should be made at the circuit design stage.
Variations in circuit performance are often modeled as an additive combination of linear variations. Each variation may typically describe a physical parameter such as an oxide thickness or a threshold voltage. A statistical transistor model may have several mismatch parameters to model its mismatch variations. However, simple linear sensitivity analysis does not provide enough information for designers to fully optimize the design. It provides only sensitivity coefficients for each mismatch parameter, and does not provide information on which particular device in a circuit design has the highest impact on overall circuit performance.
The computational expense of including circuit performance variation analysis in a design cycle can be significant or even prohibitive with current methods. The simulation time of simple OFAT (one-factor-at-a-time) sensitivity analysis generally depends on the number of devices in a circuit multiplied by the number of different mismatch parameters for each. For example, ten mismatch parameters and a thousand devices would require at least 10001 Monte Carlo circuit simulations in current OFAT sensitivity analysis schemes.
Accordingly, the inventors have identified a need for identifying important mismatch variation contributions from devices in a circuit design, and with significantly less computational expense than is required for traditional multivariate linear regression.